TU Delft
Year
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NEDERLANDSENGLISH
Organization
2011/2012 Electrical Engineering, Mathematics and Computer Science Master Computer Science
IN4340
Embedded Computer Architecture
ECTS: 5
Responsible Instructor
Name E-mail
Dr. S.D. Cotofana    S.D.Cotofana@tudelft.nl
Dr. A.M. Molnos    A.M.Molnos@tudelft.nl
Instructor
Name E-mail
Dr.ir. D.V. Borodin    D.V.Borodin-2@tudelft.nl
Dr. A.M. Molnos    A.M.Molnos@tudelft.nl
Practical Coordinator
Name E-mail
A. Beyranvand Nejad    A.BeyranvandNejad@tudelft.nl
Ir. A.T. Nelson    A.T.Nelson@tudelft.nl
Contact Hours / Week x/x/x/x
4/0/0/0
Education Period
1
Start Education
1
Exam Period
1
2
Course Language
English
Expected prior knowledge
Computer Architecture and Organization (ET2608 or an equivalent course on computer architecture) - processor architecture and organization, instruction set architecture, pipeline organization.
C programming.
Parts
Theoretical course and practical laboratory.
The laboratory emphasis on the practical utilization of an embedded, tiled, Multi-Processor System-on-a-Chip (MPSoC) platform, prototyped on an FPGA board. The student will become acquainted with various details of the MPSoC platform, i.e., processor-tiles, local and distributed shared memory blocks, Direct Memory Access (DMA), and interfacing to the outside world. Students will work in groups of 3, and will write C programs for each of the MPSoC cores and will run those programs on the FPGA prototype of the platform.
Course Contents
The course emphasises on theoretical aspects and practical trade-offs of computer architecture with focus on embedded systems. It covers concepts and various topics related to instruction set principles, instruction sets targeted at media and signal processing, reduced code size, pipelining, dynamic and static exploitation of Instruction-Level Parallelism (ILP), superscalar processors, out-of-order execution, branch prediction, speculative execution, predication, VLIW processors and compiler support for exposing ILP, advanced memory hierarchies, pre-fetching, embedded multiprocessors, energy consumption, and real-time performance.
Study Goals
1. The student can operate with concepts and notions related to:
- Instruction sets: characteristics, functions, formats, addressing modes;
- Processor structure, functions, and pipelining;
- Instruction level parallelism and its static and dynamic exploitation;
- Distributed memory hierarchy;
- Multiprocessors.
2. Given a set of functional and non-functional requirements, the student can select the most appropriate architecture among a set of different architectures of modern microprocessors.
3. She/he can optimize code for a particular processor using, e.g., code scheduling and loop unrolling.
4. She/he can perform design space exploration and quantify design decisions in terms of performance, energy consumption, cost, flexibility, programmability, predictability for various processor and multiprocessors building blocks and architecture features, e.g., instruction set, predication vs. speculation, cache vs. scratch-pad memory, in-order/out-of-order execution, message passing vs. shared memory, etc.
Education Method
Lectures, homework, and lab.
Literature and Study Materials
J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach, 4th edition, Morgan Kaufman, 2007, ISBN 0123704901.
Example exams with solutions (available on Blackboard).

A set of high-impact articles and presentations on embedded computer architecture trends and practices (available on Blackboard).
IEEE Explore
Assessment
Exam, homework assignment, and lab contribute to the final grade as follows:
1. Written open book exam - 60% of the final grade;
2. Homework assignment - 15% of the final grade;
3. Practical assignment (lab.) - 25% of the final grade;

Permitted Materials during Tests
The exam is open book. Books on computer architecture, computer organisation and lecture slides are allowed during the exams.