TU Delft
Year
print this page print this page     
NEDERLANDSENGLISH
Organization
2017/2018 Electrical Engineering, Mathematics and Computer Science Master Electrical Engineering
ET4076-11
VLSI Test Technology & Reliability
ECTS: 5
Responsible Instructor
Name E-mail
Prof.dr. S. Hamdioui    S.Hamdioui@tudelft.nl
Instructor
Name E-mail
Dr.ir. Z. Al-Ars    Z.Al-Ars@tudelft.nl
Contact Hours / Week x/x/x/x
0/0/3/0
Education Period
3
Start Education
3
Exam Period
3
Course Language
English
Course Contents
With the continuous scaling of transistor feature sizes, the VLSI chip density is exponentially increasing. This results in a significant complexity of today's and future VLSI technology; such a complexity has reached the point where billions of transistors are integrated on a single chip (as it is the case for System on Chip). To guarantee customer's satisfaction, produced VLSI chips have to be reliable and fully tested. Verification and production testing represent 50 to 60% of the chips production total cost, and are now the biggest cost of the technology. It has been known for a while that tackling problems associated with testing VLSI chips at earlier design stage levels significantly reduces the testing cost. Thus it is important for hardware designers to be exposed to concepts of VLSI testing which can help them design better products at lower cost.

To get a feeling about how important is test technology, you can imagine that just (functionally) testing of a 64bit adder (no flips flops) at 1GHz will cost 585 years! What about today’s chips with millions of flip flips? What are the practical and the efficient ways to deal with testing of VLSI chips?

This course is an introduction to the field of digital systems testing, which is an integral part of IC design and manufacturing. The topics discussed are: Importance of VLSI Testing, Test process and Automatic Test Equipment, Defects versus Fault Models, Fault Simulation, Logic Simulation, Combinational Circuit Testing, Sequential Circuit Testing, Memory Testing, Design-for-Testability, Scan Design, Boundary Scan, Built-in-Self Test, Delay Test, Current Testing and Reliability.
Study Goals
At the end of the course students should be able to perform the following:
- Describe the importance of VLSI testing and reliability, its impact on the total cost and the quality of the designed product.
- Point out the strong correlation between VLSI Design and Test
- Describe the silicon/ transistor/ interconnect defect mechanisms and the way they behave at the electrical/functional level and how they are tested using fault models and test algorithms
- Examine different test methodologies for logic and sequential circuits, their advantages, disadvantages, cost, limitations, etc.
- Analyze different Design-for-Testability DFTť methodologies, their advantages, disadvantages, cost and limitations
- State the trends and challenges in VLSI Test technology and Reliability
- Develop test algorithms and DFT techniques for digital circuits
- Better understand the weaknesses of digital systems and do research on VLSI Test Technology
- Become a better VLSI designer, a better test engineer/ product engineer
Education Method
Lectures and lab
Literature and Study Materials
Lecture Notes + Book “Essential of Electronic Testing” (by M.L. Bushnell and V.D. Agrawal, ISBN 0-7923-799-1-8)
Assessment
Assignments + DFT lab + "group" Oral examination