TU Delft
print this page print this page     
2017/2018 Electrical Engineering, Mathematics and Computer Science Master Electrical Engineering
System Design with HDLs
Responsible Instructor
Name E-mail
Dr.ir. J.S.S.M. Wong    J.S.S.M.Wong@tudelft.nl
Contact Hours / Week x/x/x/x
Education Period
Start Education
Exam Period
Course Language
Required for
Computer Arithmetic (ET8019)
Reconfigurable Computing Design (ET4370)
Expected prior knowledge
Basic course on logic design.
Course Contents
As system design often requires the utilization of hardware description languages we concentrate on such a language, i.e., VHDL and their associated simulation and synthesis tools. This course provides students with the background one may require in order to understand, modify, develop and debug VHDL system designs. Covered issues are related to VHDL language constructs as well as to the utilization of simulation and synthesis tools. The addressed topics include among others the following: hardware modeling, simulation, and synthesis; behavioral and component descriptions; signals and entities; delay models; VHDL language constructs; basic I/O; identifiers, data types, and operators.
Study Goals
The study goals of this course are the following:
- the students understand the theory behind hardware description languages
- the students are accustomed to the general syntax of VHDL
- the students are able to describe simple combinational and sequential logic circuits
- the students are familiar with at least one VHDL simulation program, i.e., preferably Modelsim
- the students are capable of describing a simple 2-stage processor pipeline design using behavioral VHDL
- the students are capable of describing a 32-bit modified Baugh-Wooley multiplier design using structural VHDL
- the students are capable to explain their designs and VHDL modeling choices
Education Method
The theory of hardware description languages and syntax of VHDL are transferred via lectures. In the same lectures, code examples are given of simple combinational and sequential logic circuits.

In a lab, hands-on experience with the Modelsim simulator is gained via a tutorial and several simple exercises are given to students to prepare them for the larger two assignments.

The larger two assignments require the students (in groups of 2) to give a behavioral description of a 2-stage processor pipeline and a structural description of a 32-bit modified Baugh-Wooley multiplier. Both assignments are assessed via an oral exam in which students have to present their designs and relate them to specific VHDL code sections.
Literature and Study Materials
* Attendance of the lab is obligatory in which students have to follow a tutorial and finish some small exercises.
* The final pass/fail course result will be based on an oral exam in which two assignments will be assessed in detail. The assignments can be done by a pair of students.
** VHDL knowledge is a prerequisite for the practical part of the compulsory course Computer Arithmetic (ET8019). Thus this course is strongly recommended to students who do not have any experience in VHDL based designs or who believe that their VHDL knowledge should be improved.